•   +91 9035261596
  •   ramaiah-skill.rsa@msruas.ac.in
Faculty Photo

Contact

  • Email
    program.manager.rsa@msruas.ac.in
  • Phone
    +91 7975781168

Mr. Raghavendra M

Head

Department
VLSI SoC Design & Embedded System Design

  • Raghavendra M is an accomplished electronics and communication engineer with 16 years of academic, research, and industry experience. He holds an M.Tech in Digital Electronics and Advanced Communication and a B.E in Electronics and Communication, establishing a robust foundation in both theoretical and practical aspects of the field.

  • Throughout his career, he has taken on impactful roles—from serving as a Learning and Development Manager at Chipedge Technologies to holding esteemed professorial positions at institutions such as PES University and Jain University. His research interests focus on analog/mixed-signal design, low-power VLSI design, FPGA-based embedded systems, and ASIC prototyping on FPGA, and he has published multiple papers in international conferences and journals.

  • In addition to his research and teaching, Raghavendra has extensive experience in delivering courses on Hardware Description Languages (Verilog & VHDL), Microelectronics, CMOS VLSI, Analog Integrated Circuits, and VLSI Testing and Verification.

  • He is proficient with leading EDA tools such as Xilinx Vivado, Cadence, and Mentor Graphics, and has experience with evaluation boards like Basys3, further showcasing his practical expertise in the field.

Qualifications

  • • M.Tech in Digital Electronics and Advanced Communication from 2008-2010
    Manipal Institute of Technology, Manipal University
  • • B.E in Electronics and Communication from 2001-2005
    PES University- RR Campus (Formerly PESIT)
  • • Diploma in Electronics and Communication from 1997-2001
    MN Technical Institute

Experience

  • Total Years of Experience 16 Years

  • Academic, Industry and Research Experience

  • • Ramaiah Skill Academy, Ramaiah University of Applied Sciences
    Head and Program Manager
    Dec 2024 to Till Date
  • • Chipedge Technologies
    Learning and Development Manager
    May 2022- Oct 2024
  • • PES University – EC Campus (Formally PESIT-South Campus)
    Assistant Professor
    Electronics and Communication
    July 2011 to Jan 2022
  • • School of Engineering & Technology, Jain University
    Assistant Professor
    Electronics and Communication
    August 2010 to July 2011
  • • PES Polytechnic
    Lecturer in Department of ECE
    August 2007 to Jun 2008

Research Interest

  • • Analog/Mixed-Signal Design
  • • Low-Power VLSI Design
  • • Embedded Systems Design with FPGAs
  • • ASIC Prototyping on FPGA

Publication

  1. Hazrath Patil, M Raghavendra, “Low power dynamic compactor for 4 bit Flash ADC,” International Journal of Service Computing And Computational Intelligence, ICCIC1600104
  2. Rahul P V, Anusha Kulkarni, Sohail Sankanur and Raghavendra M, “Reduced Comparators for Low Power Flash ADC using TSMC018,” International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
  3. Rohit J, Raghavendra M, “Implementation of 32-bit RISC processors without interlocked Pipelining on Artix-7 FPGA Board,” 2017 International Conference on Circuits, Controls, and Communications (CCUBE 2017)
  4. Vamshi, Raghavendra M, “Low Power, High Speed 4-Dimension FinFET SRAM,” International Conference Of Emerging Technologies 2021
  5. Sapna, Raghavendra M, “Comparative analysis of MOSFET and FINFET DRAM N*N Array,” International Conference Of Emerging Technologies 2021